FIELD OF THE INVENTION
The invention relates to a circuit apparatus for evaluating the data content of memory cells of an integrated semiconductor memory, which memory cells are disposed along bit lines and word lines.
The recovery of information from a memory cell constitutes a significant problem in the course of development and during operation of a DRAM. On the one hand, the information in a cell is represented by an extremely small capacitance. On the other hand, the capacitance is often reduced further by a wide variety of influences. It is necessary to amplify the small amount of charge such that the correct information can be reconstructed.
In many configurations known to date, the interference produced on account of capacitive coupling in the course of assessing the cell signal (sensing) on the neighboring bit lines is tolerated. However, the configurations require a larger cell capacitance. Other configurations use so-called twisted bit lines, but they take up valuable chip space.